1. Field of the Invention
The invention relates to a phase locked loop, more particularly to a phase locked loop capable of dynamic phase compensation during frequency locking.
2. Description of the Related Art
Phase locked loops are commonly used in a wireless communication system requiring frequencies with high accuracy FIG. 1 illustrates a conventional phase locked loop 1 that includes a phase/frequency detector 11, a charge pump 12, a filter 13, a voltage controlled oscillator 15, and a frequency divider 15 connected in a feedback loop.
The phase/frequency detector 11 detects a reference signal (Fref), and a divided feedback signal (Fdiv) generated by the frequency divider 15 through frequency division on an output signal (Fout) from the voltage controlled oscillator 14, and outputs a phase detecting output having a first pulse signal (UP) indicating a phase of the reference signal (Fref), and a second pulse signal (DN) indicating a phase of the divided feedback signal (Fdiv). The charge pump 12 outputs a current signal to the filter 13 in response to the first and second pulse signals (UP, DN). The filter 13 outputs a control voltage signal in response to the current signal from the charge pump 12. The voltage controlled oscillator 14 generates the output signal (Fout) corresponding to the reference signal (Fref) in response to the control voltage signal from the filter 13. For the conventional phase locked loop 1, phase difference between the reference signal (Fref) and the divided feedback signal (Fdiv) is compensated using a known frequency negative feedback manner until the reference signal (Fref) and the divided feedback signal (Fdiv) are in-phase.
To meet high quality requirements of a communication system, the conventional phase locked loop 1 must be capable of fast locking and suppressing noise. However, in the design of the conventional phase locked loop 1, there is a trade-off between fast locking and noise suppression capability. Because, for high data transmission capability, the conventional phase locked loop 1 has to have a large bandwidth sufficient to speed up frequency locking. However, due to loop characteristics, low-frequency noise from the phase/frequency detector 11, the charge pump 12, the filter 13 and the frequency divider 15 must be effectively suppressed using a smaller bandwidth. Therefore, it becomes a very critical issue to develop a phase locked loop capable of fast locking using a narrow bandwidth.
To solve the foregoing problem, another conventional phase locked loop (not shown) using a known bandwidth switching manner has been proposed. FIG. 2 illustrates a control voltage signal for a voltage controlled oscillator of the conventional phase locked loop using frequency switching, and indicates that the phase locked loop is operable between an unlocked state, where wide bandwidth operation is performed to speed up frequency locking, and a locked state, where narrow bandwidth operation is performed to suppress noises. The unlocked state contains a frequency locking stage (I) and a phase compensating stage (II). As shown in FIG. 3, since a phase difference between a reference signal (Fret) and a divided feedback signal (Fdiv) gradually increases during the frequency locking stage (I), it takes a longer time period to compensate the phase difference between the reference signal (Fref) and the divided feedback signal (Fdiv) during the phase compensating stage (II), thereby resulting in a longer locking time period. As a result, the conventional phase locked loop using frequency switching cannot achieve fast locking.